D at a S h e e t , D S 3 , M ay 2 00 2
SCOUT-DX
Siemens Codec with 2-Wire Data
Transceiver Featuring
Speakerphone Function
PSB 21373 Version 1.1
Wire d
Communications
N e v e r
s t o p
t h i n k i n g .
Data Sheet
Revision History:
2002-05-13
Previous Version:
Prel. Data Sheet, DS2
DS 3
Page
Subjects (major changes since last revision)
Page 32
Figure 10 with clock signals added
Page 62
BCL=’ 0’ changed to BCL=’1’
Page 80
BCL changed from ’low’ to ’high’
Page 106
Note regarding AXI input added
Page 143
Recommendation regarding CRAM programming modified
Page 158
BCL is inverted compared to last description (DS1); figure 75 added
Page 161
’Rising’ BCL edge changed to ’falling’ edge
Page 232
Figure 80 (BCL)modified
Page 234
SDX output delay added
Page 236
DC charateristics of transceiver modified
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com.
Edition 2002-05-13
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 11/24/04.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
PSB 21373
Table of Contents
Page
1
1.1
1.2
1.3
1.4
1.5
1.6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Pin Definitions and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
General Functions and Device Architecture . . . . . . . . . . . . . . . . . . . . . . . .19
2
2.1
2.1.1
2.1.1.1
2.1.2
2.1.3
2.2
2.2.1
2.2.2
2.2.2.1
2.2.2.1.1
2.2.2.1.2
2.2.2.1.3
2.2.2.1.4
2.2.3
2.2.3.1
2.2.3.2
2.2.4
2.2.4.1
2.2.4.2
2.2.4.3
2.2.4.4
2.2.4.5
2.2.4.6
2.2.5
2.2.5.1
2.2.6
2.2.7
2.2.7.1
2.2.8
2.3
2.3.1
2.3.2
2.3.3
2.3.4
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Programming Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Interrupt Structure and Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Microcontroller Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
IOM-2 Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
IOM-2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Controller Data Access (CDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Looping and Shifting Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Monitoring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Monitoring TIC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Synchronous Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Serial Data Strobe Signal and strobed Data Clock . . . . . . . . . . . . . . . . .44
Serial Data Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Strobed IOM Bit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
IOM-2 Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Error Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
MONITOR Channel Programming as a Master Device . . . . . . . . . . . .54
MONITOR Channel Programming as a Slave Device . . . . . . . . . . . . .54
MONITOR Time-Out Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
MONITOR Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
C/I Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
CIC Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Settings after Reset (see also chapter 7.3) . . . . . . . . . . . . . . . . . . . . . . .59
D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
TIC Bus D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . .60
Activation/Deactivation of IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . .62
Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Burst Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Transceiver Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Data Transfer and Delay between IOM and Line Interface . . . . . . . . . . .67
Control of the Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Data Sheet
3
2002-05-13
PSB 21373
Table of Contents
2.3.4.1
2.3.4.1.1
2.3.4.1.2
2.3.4.1.3
2.3.4.1.4
2.3.4.1.5
2.3.4.1.6
2.3.4.1.7
2.3.4.1.8
2.3.4.2
2.3.4.2.1
2.3.4.2.2
2.3.5
2.3.6
2.3.7
2.3.7.1
2.3.7.2
2.3.8
2.3.9
2.3.10
3
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.2
3.2.1
3.2.1.1
3.2.1.2
3.2.1.3
3.2.2
3.3
3.3.1
3.3.1.1
3.3.1.2
3.3.1.3
3.3.2
3.4
3.5
3.5.1
Page
Internal Layer-1 State machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
State Transition Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
C/I Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Receive Infos on the Line (Downstream) . . . . . . . . . . . . . . . . . . . . .73
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
C/I Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Transmit Infos on the Line (Upstream) . . . . . . . . . . . . . . . . . . . . . .75
Example of Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . .76
External Layer-1 State machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Activation initiated by the Terminal (TE, SCOUT-DX) . . . . . . . . . . .78
Activation initiated by the Line Termination LT . . . . . . . . . . . . . . . .79
Level Detection Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Transceiver Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Line Transceiver Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Test Signals on the Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Line Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
HDLC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Message Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Non-Auto Mode (MDS2-0 = ’01x’) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Transparent Mode 0 (MDS2-0 = ’110’). . . . . . . . . . . . . . . . . . . . . . . . . . .86
Transparent Mode 1 (MDS2-0 = ’111’). . . . . . . . . . . . . . . . . . . . . . . . . . .86
Transparent Mode 2 (MDS2-0 = ’101’). . . . . . . . . . . . . . . . . . . . . . . . . . .86
Extended Transparent Mode (MDS2-0 = ’100’). . . . . . . . . . . . . . . . . . . .86
Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Structure and Control of the Receive FIFO . . . . . . . . . . . . . . . . . . . . . . .86
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Possible Error Conditions during Reception of Frames . . . . . . . . . . . .90
Data Reception Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Receive Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Structure and Control of the Transmit FIFO . . . . . . . . . . . . . . . . . . . . . .95
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Possible Error Conditions during Transmission of Frames . . . . . . . . .97
Data Transmission Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Transmit Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Access to IOM Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Extended Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Data Sheet
4
2002-05-13
PSB 21373
Table of Contents
Page
3.5.2
3.6
3.7
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
HDLC Controller Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
4
4.1
4.1.1
4.2
4.2.1
4.2.2
4.2.3
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.4
4.4.1
4.4.2
4.4.3
4.4.3.1
4.4.3.2
4.4.4
4.4.4.1
4.4.4.2
4.4.4.3
4.4.5
4.4.6
4.5
4.6
4.7
4.8
4.8.1
4.8.1.1
4.8.2
4.8.2.1
4.8.3
Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Analog Front End (AFE) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
AFE Attenuation Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Signal Processor (DSP) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Transmit Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Receive Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Programmable Coefficients for Transmit and Receive . . . . . . . . . . . . .112
Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Four Signal Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Sequence Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Control Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Tone Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Tone Level Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
DTMF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Speakerphone Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Attenuation Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Speakerphone Test Function and Self Adaption . . . . . . . . . . . . . . . . . .123
Speech Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Background Noise Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Speech Comparators (SC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Speech Comparator at the Acoustic Side (SCAE) . . . . . . . . . . . . . . .127
Speech Comparator at the Line Side (SCLE) . . . . . . . . . . . . . . . . . .130
Automatic Gain Control of the Transmit Direction (AGCX) . . . . . . . .132
Automatic Gain Control of the Receive Direction (AGCR) . . . . . . . . . . .135
Speakerphone Coefficient Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Controlled Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
Voice Data Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
Programming of the Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Indirect Programming of the Codec (SOP, COP, XOP) . . . . . . . . . . . .143
Description of the Command Word (CMDW) . . . . . . . . . . . . . . . . . . .144
Direct Programming of the Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
CRAM Back-Up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
Reference Tables for the Register and CRAM Locations . . . . . . . . . . .148
5
5.1
5.1.1
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Jitter on IOM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Data Sheet
5
2002-05-13
PSB 21373
Table of Contents
5.1.2
5.1.3
Page
Jitter on the Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Jitter on MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
6
6.1
6.2
6.3
6.4
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
Reset Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
External Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
Software Reset Register (SRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
Pin Behavior during Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10
7.1.11
7.1.12
7.1.13
7.1.14
7.1.15
7.1.16
7.1.17
7.1.18
7.1.19
7.1.20
7.1.21
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
HDLC Control and C/I Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
RFIFO - Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
XFIFO - Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
ISTAH - Interrupt Status Register HDLC . . . . . . . . . . . . . . . . . . . . . . . .170
MASKH - Mask Register HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
STAR - Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
CMDR - Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
MODEH - Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
EXMR- Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
TIMR - Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
SAP1 - SAPI1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
RBCL - Receive Frame Byte Count Low . . . . . . . . . . . . . . . . . . . . . . . .177
SAP2 - SAPI2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
RBCH - Receive Frame Byte Count High . . . . . . . . . . . . . . . . . . . . . . .178
TEI1 - TEI1 Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
RSTA - Receive Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
TEI2 - TEI2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
TMH -Test Mode Register HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
CIR0 - Command/Indication Receive 0 . . . . . . . . . . . . . . . . . . . . . . . . .182
CIX0 - Command/Indication Transmit 0 . . . . . . . . . . . . . . . . . . . . . . . . .183
CIR1 - Command/Indication Receive 1 . . . . . . . . . . . . . . . . . . . . . . . . .183
CIX1 - Command/Indication Transmit 1 . . . . . . . . . . . . . . . . . . . . . . . . .184
Transceiver, Interrupt and General Configuration Registers . . . . . . . . . . .185
TR_CONF0 - Transceiver Configuration Register . . . . . . . . . . . . . . . . .185
TR_CONF1 - Receiver Configuration Register . . . . . . . . . . . . . . . . . . .186
TR_CONF2 - Transmitter Configuration Register . . . . . . . . . . . . . . . . .186
TR_STA - Transceiver Status Register . . . . . . . . . . . . . . . . . . . . . . . . .187
TR_CMD - Transceiver Command Register . . . . . . . . . . . . . . . . . . . . .188
ISTATR - Interrupt Status Register Transceiver . . . . . . . . . . . . . . . . . .189
MASKTR - Mask Transceiver Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .189
ISTA - Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
MASK - Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
MODE1 - Mode1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
Data Sheet
6
2002-05-13
PSB 21373
Table of Contents
Page
7.2.11
7.2.12
7.2.13
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
7.3.11
7.3.12
7.3.13
7.3.14
7.3.15
7.3.16
7.3.17
7.3.18
7.3.19
7.3.20
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10
7.4.11
7.4.12
7.4.13
7.4.14
MODE2 - Mode2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
ID - Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
SRES - Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
IOM-2 and MONITOR Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
CDAxy - Controller Data Access Register xy . . . . . . . . . . . . . . . . . . . . .195
XXX_TSDPxy - Time Slot and Data Port Selection for CHxy . . . . . . . .196
CDAx_CR - Control Register Controller Data Access CH1x . . . . . . . . .197
CO_CR - Control Register Codec Data . . . . . . . . . . . . . . . . . . . . . . . . .198
TR_CR - Control Register Transceiver Data . . . . . . . . . . . . . . . . . . . . .198
HCI_CR - Control Register for HDLC and CI1 Data . . . . . . . . . . . . . . .199
MON_CR - Control Register Monitor Data . . . . . . . . . . . . . . . . . . . . . .199
SDSx_CR - Control Register Serial Data Strobe x . . . . . . . . . . . . . . . .200
IOM_CR - Control Register IOM Data . . . . . . . . . . . . . . . . . . . . . . . . . .201
MCDA - Monitoring CDA Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
STI - Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .203
ASTI - Acknowledge Synchronous Transfer Interrupt . . . . . . . . . . . . . .204
MSTI - Mask Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . .204
SDS_CONF - Configuration Register for Serial Data Strobes . . . . . . . .205
MOR - MONITOR Receive Channel . . . . . . . . . . . . . . . . . . . . . . . . . . .205
MOX - MONITOR Transmit Channel . . . . . . . . . . . . . . . . . . . . . . . . . . .205
MOSR - MONITOR Interrupt Status Register . . . . . . . . . . . . . . . . . . . .206
MOCR - MONITOR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .207
MSTA - MONITOR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
MCONF - MONITOR Configuration Register . . . . . . . . . . . . . . . . . . . . .208
Codec Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
General Configuration Register (GCR) . . . . . . . . . . . . . . . . . . . . . . . . .209
Programmable Filter Configuration Register (PFCR) . . . . . . . . . . . . . .210
Tone Generator Configuration Register (TGCR) . . . . . . . . . . . . . . . . . .211
Tone Generator Switch Register (TGSR) . . . . . . . . . . . . . . . . . . . . . . .212
AFE Configuration Register (ACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
AFE Transmit Configuration Register (ATCR) . . . . . . . . . . . . . . . . . . . .214
AFE Receive Configuration Register (ARCR) . . . . . . . . . . . . . . . . . . . .215
Data Format Register (DFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
Data Source Selection Register (DSSR) . . . . . . . . . . . . . . . . . . . . . . . .217
Extended Configuration (XCR) and Status (XSR) Register . . . . . . . . . .218
Mask Channel x Register (MASKxR) . . . . . . . . . . . . . . . . . . . . . . . . . . .220
Test Function Configuration Register (TFCR) . . . . . . . . . . . . . . . . . . . .221
CRAM Control (CCR) and Status (CSR) Register . . . . . . . . . . . . . . . . .222
CRAM (Coefficient RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
8
8.1
8.1.1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
Electrical Characteristics (general) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
Data Sheet
7
2002-05-13
PSB 21373
Table of Contents
Page
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.7.1
8.1.8
8.2
8.3
8.3.1
8.3.2
8.3.3
DC-Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
IOM-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
Microcontroller Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
Serial Control Interface (SCI) Timing . . . . . . . . . . . . . . . . . . . . . . . . .234
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
Electrical Characteristics (Transceiver) . . . . . . . . . . . . . . . . . . . . . . . . . .236
Electrical Characteristics (Codec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
DC Characterisics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
Analog Front End Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .240
Analog Front End Output Characteristics . . . . . . . . . . . . . . . . . . . . . . .240
9
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
Data Sheet
8
2002-05-13
PSB 21373
1
Overview
The SCOUT™-DX integrates all necessary functions for the completion of a cost effective
digital voice terminal solution.
The SCOUT-DX combines the functionality of the ARCOFI®-SP PSB 2163 (Audio
Ringing Codec Filter with Speakerphone) and a two wire line interface1) on a single chip.
The SCOUT-DX is suited for the use in basic PBX voice terminals just as, in combination
with an additional device on the modular IOM®-2 interface, in high end featurephones
e.g. with acoustic echo cancellation.
The transceiver implements the subscriber access functions for a digital terminal to be
connected to the two wire line interface. It covers complete layer-1 and basic layer-2
functions for digital terminals.
The codec performs encoding, decoding, filtering functions and tone generation (ringing,
audible feedback tones and DTMF signal). An analog front end offers three analog inputs
and two analog outputs with programmable amplifiers.
The IOM-2 interface allows a modular design with functional extensions (e.g. acoustic
echo cancellation, modem extension) by connecting other voice/data devices to the
SCOUT-DX.
A serial microcontroller interface (SCI) is supported.
The SCOUT-DX is a CMOS device offered in a P-MQFP-44 package and operates with
a 5 V supply.
1)
compatible to TP3406 of National
Data Sheet
Semiconductor Corporation
9
2002-05-13
Siemens Codec with 2-Wire Data Transceiver
Featuring Speakerphone Function
SCOUT-DX
PSB 21373
Version 1.1
1.1
CMOS
Features
• Serial control interface (SCI)
• IOM-2 interface in TE mode, single/double clock,
two serial data strobe signals
• Various possibilities of microcontroller data access,
data control and data manipulation to all IOM-2
timeslots
• Power supply 5 V
• Monitor channel handler (master/slave)
P-MQFP-44-1
• Sophisticated power management for restricted power mode
• Programmable microcontroller clock output and reset (input/output) pins
• Advanced CMOS technology
Transceiver part
• Two wire transceiver with AMI coded 2B+D channels for loop length up to 1.8 km
(6 kft)
• Conversion of the frame structure between the two wire line interface and IOM-2
• Receive timing recovery
• Continuously adapted receive thresholds
• Activation and deactivation procedures with automatic activation from power down
state
• HDLC controller. Access to B1, B2 or D channels or the combination of them e.g.
for 144 kbit data transmission (2B+D)
• FIFO buffer with 64 bytes per direction and programmable FIFO thresholds for
efficient transfer of data packets
Type
Package
PSB 21373
P-MQFP-44-1
Data Sheet
10
2002-05-13
PSB 21373
• Implementation of IOM-2 MONITOR and C/I-channel protocol to control peripheral
devices
• Realization of layer 1 state machine in software possible
• Watchdog timer
• Programmable reset sources
• Test loops and functions
Codec part
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Applications in digital terminal equipment featuring voice functions
Digital signal processing performs all CODEC functions
Fully compatible with the ITU-T G.712 and ETSI (NET33) specification
PCM A-Law/µ-Law (ITU-T G.711) and 8/16-bit linear data; maskable codec data
Flexible configuration of all internal functions
Three analog inputs for the handset microphone , the speakerphone and the headset
Two differential outputs for a handset ear piece (200 Ω) and a loudspeaker (50 Ω)
Flexible test and maintenance loopbacks in the analog front end and the digital signal
processor
Independent gain programmable amplifiers for all analog inputs and outputs
Full digital speakerphone and loud hearing support without any external components
(speakerphone test and optimization function is available)
Enhanced voice data manipulation for features like:
- Three-party conferencing
- Voice monitoring
Two transducer correction filters
Side tone gain adjustment
Flexible DTMF, tone and ringing generator
Direct and indirect CRAM access
Data Sheet
11
2002-05-13
PSB 21373
33 32 31 30 29
28 27 26
BCL
DCL
FSC
VSSPLL
VDDPLL
reserved
reserved
VSSL
VDDL
LIa
Pin Configuration
LIb
1.2
25 24 23
reserved
34
22
DU
reserved
35
21
DD
VDDA
36
20
SD X
V SSA
37
19
SD R
V R EF
38
18
SC LK
BG R EF
39
17
V SSD
AXI
40
16
V DDD
M IN 2
41
15
EAW
M IP2
42
14
XTAL1
M IN 1
43
13
XTAL2
M IP1
44
12
M C LK
2
3
4
5
6
7
8
9
10 11
LSP
VSSP
LSN
HOP
HON
CS
INT
RST
RSTO/SDS2
SDS1
1
VDDP
S C O U T -D X
PSB 21373
P -M Q F P -4 4
mqfp44_pin_d
Figure 1
Pin Configuration
Data Sheet
12
2002-05-13
PSB 21373
1.3
Logic Symbol
IOM-2 Interface
5
VDD
5
VSS
DD
VREF
DU FSC DCL BCL SDS1 RSTO/
SDS2
BGREF
RST
Analog Front End
AXI
MIP1
MIN1
LIa
MIP2
LIb
MIN2
XTAL2
HOP
HON
XTAL1
Line Interface
15.36 MHz
EAW
LSP
LSN
CS
INT MCLK SCLK SDR SDX
Serial Control Interface (SCI)
VDD:
5 separate power pins
(VDDL,VDDD,VDDA,VDDP,VDDPLL)
VSS:
5 separate ground pins
(VSSL,VSSD,VSSA,VSSP,VSSPLL)
logsym_d
Figure 2
Logic Symbol of the SCOUT-DX in P-MQFP-44
Data Sheet
13
2002-05-13
PSB 21373
1.4
Pin Definitions and Function
Table 1
Pin No.
Symbol
Input (I)
Output (O)
Open Drain
(OD)
Function
Power supply (5 V ± 5 %)
31
16
36
1
27
30
17
37
3
26
VDDL
VDDD
VDDA
VDDP
VDDPLL
VSSL
VSSD
VSSA
VSSP
VSSPLL
–
Supply voltage for line driver
–
Supply voltage for digital parts
–
Supply voltage for analog parts
–
Supply voltage for loudspeaker
–
Supply voltage for internal PLL
–
Ground for line driver
–
Ground for digital parts
–
Ground for analog parts
–
Ground for loudspeaker
–
Ground for internal PLL
IOM-2 Interface
21
DD
I/OD/O
Data Downstream
22
DU
I/OD/O
Data Upstream
25
FSC
I/O
Frame Synchronization Clock (8 kHz)
24
DCL
I/O
Data Clock (double clock, 1.536 MHz)
23
BCL
O
Bit Clock (768kHz)
11
SDS1
O
Programmable strobe signal or bit clock
10
RSTO/
SDS2
OD
O
Reset Output (active low)
Strobe signal for each IOM® time slot and/or
D channel indication (programmable)
RESET
9
Data Sheet
RST
I
Reset (active low)
14
2002-05-13
PSB 21373
Table 1
Pin No.
Symbol
Input (I)
Output (O)
Open Drain
(OD)
Function
Transceiver
32
33
LIa
LIb
I/O
I/O
Line Interface
13
14
XTAL2
XTAL1
OI
I
Oscillator output
Oscillator or 15.36 MHz input
15
EAW
I
External Awake.
A low level on this input starts the oscillator from
the power down state and generates a reset
pulse if enabled (see chapter 7.2.10)
Microcontroller Interface
7
CS
I
Chip Select (active low)
8
INT
OD
Interrupt request (active low)
12
MCLK
O
Microcontroller Clock
18
SCLK
I
Clock for the serial control interface
19
SDR
I
Serial Data Receive
20
SDX
OD/O
Serial Data Transmit
Data Sheet
15
2002-05-13
PSB 21373
Table 1
Pin No.
Symbol
Input (I)
Output (O)
Open Drain
(OD)
Function
Analog Frontend
38
VREF
O
2.4 V Reference voltage for biasing external
circuitry.
An external capacity of ≥ 100 nF has to be
connected.
39
BGREF
I/O
Reference Bandgap voltage for internal
references.
An external capacity of ≥ 22 nF has to be
connected.
40
AXI
I
Single-ended Auxiliary Input
44
43
MIP1
MIN1
I
I
Symmetrical differential Microphone Input 1
42
41
MIP2
MIN2
I
I
Symmetrical differential Microphone Input 2
5
6
HOP
HON
O
O
Differential Handset ear piece Output for 200 Ω
transducers
2
4
LSP
LSN
O
O
Differential Loudspeaker output for 50 Ω
Reserved Pins
28
reserved
I
This input is not used for normal operation and
must be connected to VDD.
29
reserved
I
This input is not used for normal operation and
must be connected to VSS.
34
reserved
I
This input is not used for normal operation and
must be connected to VDD.
35
reserved
I
This input is not used for normal operation and
must be connected to VDD.
Data Sheet
16
2002-05-13
PSB 21373
1.5
Typical Applications
The SCOUT-DX can be used in a variety of applications like
• PBX voice terminal with speakerphone (Figure 3)
• PBX voice terminal as featurephone with acoustic echo cancellation (Figure 4)
• PBX voice terminal with tip/ring extension (Figure 5)
SCOUT-DX
Line Interface
SCI
µC
voice_te_d
Figure 3
PBX Voice Terminal with Speakerphone
Data Sheet
17
2002-05-13
PSB 21373
Line Interface
SCOUT-DX
IOM-2
SCI
µC
ACE
vt_ace_d
Figure 4
PBX Voice Terminal as Featurephone with Acoustic Echo Cancellation
Line Interface
SCOUT-DX
IOM-2
SLIC
ARCOFI-BA
Fax
SCI
µC
vt_tipring_d
Figure 5
PBX Voice Terminal with Tip/Ring Extension
Data Sheet
18
2002-05-13
PSB 21373
1.6
General Functions and Device Architecture
Figure 6 shows the architecture of the SCOUT-DX containing the following functional
blocks:
•
•
•
•
•
•
•
•
•
Two wire line interface
Serial microcontroller interface
HDLC controller with 64 byte FlFOs per direction and programmable FIFO threshold
IOM-2 handler and interface for terminal application, MONITOR handler
Clock and timing generation
Digital PLL to synchronize IOM-2 to the line interface
Reset generation (watchdog timer)
Analog Front End (AFE) of the codec part
Digital Signal Processor (DSP) for codec/filter functions, tone generation, voice data
manipulation and speakerphone function
These functional blocks are described in the following chapters.
Data Sheet
19
2002-05-13
Int
Dec
Int
Dec
Adjustment
Digital Gain
Filter
Correction
Frequency
HON
HOP
AHO
AFE
Codec Control / Config.
DSP
Sidetone
Tone Generator
Function
D/A
A/D
LP-Filter
LSN
ALS
AMI
Speakerphone
ARCHIT-U1
MUX
AIN-
LSP
MIP2
MIN2
MIP1
MIN1
Data
R-FIFO
Controller
FIFO
Register
Microcontroller Interface
X-FIFO
Status
ver
mitter
Command
LAPD
Controller
HDLC
Recei-
HDLC
SCI
MUX
IOM-2 Handler
Trans-
Data
HDLC-
H D LC
D a ta
AXI
IOM-2 Interface
HDLC
C o n tro l
Codec
CS
VREF
SDX
Interrupt
MCLK
Reset
Handler
MONITOR
M o n ito r
D a ta
C/I
S-Data
Transc.
Control /
Config.
C/I-Data
VDDDET
M o n ito r D a ta
V REF
C o n tro lle r D a ta A c c e s s
SDR
S C LK
T IC B u s
D a ta
T IC
T IC B u s D a ta
C /I D a ta
C /I D a ta
BGREF
G e n e ra tio n
20
RSTO
RST
M CLK
IN T
VDDDET
EA
W
VDDSEL
Data Sheet
DPLL
T ra n s c e iv e r
OSC
VDDx
VSSx
DU DD FSC DCL BCL SDS1 SDS2
XTAL2
XTAL1
LIb
LIa
PSB 21373
Figure 6
Architecture of the SCOUT-DX
2002-05-13
D a ta S o u r c e S e le c tio n , V o ic e D a ta M a n ip u la tio n
(C o d in g , M a s k in g , C o n fe r e n c in g )
PSB 21373
2
Interfaces
The SCOUT-DX provides the following interfaces:
• Serial microcontroller interface together with a reset and microcontroller clock
generation.
• IOM-2 interface as an universal backplane for terminals
• Line interface towards the two wire subscriber line
• Analog Front End (AFE) as interface between the analog transducers and the digital
signal processor of the codec part
The microcontroller and IOM-2 interface are described in chapter 2.1 or 2.2
respectively. The line interface is described in the chapter 2.3, the analog front end
(AFE) in chapter 4.1
Data Sheet
21
2002-05-13
PSB 21373
2.1
Microcontroller Interface
The SCOUT-DX supports a serial microcontroller interface. For applications where no
controller is connected to the SCOUT-DX microcontroller interface programming is done
via the IOM-2 MONITOR channel from a master device. In such applications the
SCOUT-DX operates in the IOM-2 slave mode (refer to the corresponding chapter of the
IOM-2 MONITOR handler).
The interface selections are all done by pinstrapping. The possible interface selections
are listed in table 2. The selection pins are evaluated when the reset input RST is
released. For the pin levels stated in the tables the following is defined:
’High’:
dynamic pin value which must be ’High’ when the pin level is evaluated
VDD, VSS: static ’High’ or ’Low’ level
Table 2
Interface Selection
PIN
CS
Interface
Type/Mode
‘High’
Serial Control Interface
(SCI)
VSS
IOM-2 MONITOR Channel
(Slave Mode)
The mapping of all accessible registers can be found in figure 76 in chapter 7.
The microcontroller interface also consists of a microcontroller clock generation at pin
MCLK and an interrupt request at pin INT.
Data Sheet
22
2002-05-13
PSB 21373
2.1.1
Serial Control Interface (SCI)
The serial control interface (SCI) is compatible to the SPI interface of Motorola or
Siemens C510 family of microcontrollers.
The SCI consists of 4 lines: SCLK, SDX, SDR and CS. Data are transferred via the lines
SDR and SDX at the rate given by SCLK. The falling edge of CS indicates the beginning
of a serial access to the registers. Incoming data is latched at the rising edge of SCLK
and shifts out at the falling edge of SCLK. Each access must be terminated by a rising
edge of CS. Data is transferred in groups of 8-bits with the MSB first.
Figure 7 shows the timing of a one byte read/write access via the serial control interface.
Data Sheet
23
2002-05-13
PSB 21373
Figure 7
Serial Control Interface Timing
Data Sheet
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2002-05-13
PSB 21373
2.1.1.1
Programming Sequences
The principle structure of a read/write access to the SCOUT-DX registers via the serial
control interface is shown in figure 8.
write sequence:
write
byte 2
header
SDR
7
0
0 7
read sequence:
byte 3
address (command)
6
write data
0
7
0
7
0
read
byte 2
header
SDR
7
1
0 7
address (command)
6
SDX
byte 3
0
read data
Figure 8
Serial Command Structure
A new programming sequence starts with the transfer of a header byte. The header byte
specifies different programming sequences allowing a flexible and optimized access to
the individual functional blocks of the SCOUT-DX.
The possible sequences are listed in table 3 and are described afterwards.
Table 3
Header Byte Code
Header
Byte
Sequence
00H
Cmd-Data-Data-Data ARCOFI compatible,
non-interleaved
08H
ARCOFI compatible,
interleaved
40H
non-interleaved
44H
48H
Sequence Type
Adr-Data-Adr-Data
Codec reg./CRAM (indirect)
Address Range 00H-6FH
CRAM (80H-FFH)
interleaved
4CH
Data Sheet
Access to
Address Range 00H-6FH
CRAM (80H-FFH)
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Table 3
Header Byte Code (cont’d)
4AH
Read-/Write-only
Address Range 00H-6FH
4EH
(address auto
increment)
CRAM (80H-FFH)
Adr-Data-Data-Data
43H
Read-/Write-only
41H
non-interleaved
49H
interleaved
Address Range 00H-6FH
Header 00H: ARCOFI Compatible Sequence
This programming sequence is compatible to the SOP, COP and XOP command
sequences of the ARCOFI. It gives indirect access to the codec registers 60H-6FH and
the CRAM (80H-FFH). The codec command word (cmdw) is followed by a defined
number of data bytes (data n; n = 0, 1, 4 or 8). The number of data bytes depends on the
codec command word. The commands can be applied in any order and number. The
coding of the different SOP, COP and XOP commands is listed in the description of the
command word (CMDW) in chapter 4.8.
Structure of the ARCOFI compatible sequence:
defined length
00H
cmdw
data1
defined length
data n
cmd
data1
data n
Header 40H, 44H: Non-interleaved A-D-A-D Sequences
The non-interleaved A-D-A-D sequences give direct read/write access to the address
range 00H-6FH (header 40H) or the CRAM range 80H-FFH (header 44H) respectively and
can have any length. In this mode SDX and SDR can be connected together allowing
data transmission on one line.
Example for a read/write access with header 40H or 44H:
SDR
header
SDX
wradr
wrdata
rdadr
rdadr
rddata
wradr
wrdata
rdata
Header 48H, 4CH: Interleaved A-D-A-D Sequences
The interleaved A-D-A-D sequences give direct read/write access to the address range
00H-6FH (header 48H) or the CRAM range 80H-FFH (header 4CH) respectively and can
have any length. This mode allows a time optimized access to the registers by
Data Sheet
26
2002-05-13
PSB 21373
interleaving the data on SDX and SDR.
Example for a read/write access with header 48H or 4CH:
SDR
header
wradr
wrdata
rdadr
SDX
rdadr
wradr
rddata
rddata
wrdata
Header 4AH, 4EH: Read-/Write-only A-D-D-D Sequences (Address Auto increment)
The A-D-D-D sequences give a fast read-/write-only access to the address range 00H6FH (header 4AH) or the CRAM range 80H-FFH (header 4EH) respectively.
The starting address (wradr, rdadr) is autoincremented after every data byte. The
sequence can have any length and is terminated by the rising edge of CS.
Example for a write access with header 4AH or 4EH:
SDR
header
wradr
wrdata
wrdata
wrdata
wrdata
wrdata
wrdata
wrdata
(wradr)
(wradr+1)
(wradr+2)
(wradr+3)
(wradr+4)
(wradr+5)
(wradr+6)
SDX
Example for a read access with header 4AH or 4EH:
SDR
header
rdadr
SDX
rddata
rddata
rddata
rddata
rddata
rddata
rddata
(rdadr)
(rdadr+1)
(rdadr+2)
(rdadr+3)
(rdadr+4)
(rdadr+5)
(rdadr+6)
Header 43H: Read-/Write- only A-D-D-D Sequence
This mode (header 43H) can be used for a fast access to the HDLC FIFO data. Any
address (rdadr, wradr) in the range between 00h and 1F gives access to the current
FIFO location selected by an internal pointer which is automatically incremented with
every data byte following the first address byte. The sequence can have any length and
is terminated by the rising edge of CS.
Example for a write access with header 43H:
SDR
header
wradr
wrdata
wrdata
wrdata
wrdata
wrdata
wrdata
wrdata
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
SDX
Example for a read access with header 43H:
SDR
header
SDX
Data Sheet
rdadr
rddata
rddata
rddata
rddata
rddata
rddata
rddata
(rdadr)
(rdadr)
(rdadr)
(rdadr)
(rdadr)
(rdadr)
(rdadr)
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Header 41H: Non-interleaved A-D-D-D Sequence
This sequence (header 41H) allows in front of the A-D-D-D write access a noninterleaved A-D-A-D read access. This mode is useful for reading status information
before writing to the HDLC XFIFO. The termination condition of the read access is the
reception of the wradr. The sequence can have any length and is terminated by the rising
edge of CS.
Example for a read/write access with header 41H:
SDR
header
rdadr
SDX
rdadr
rddata
wradr
wrdata
wrdata
wrdata
(wradr)
(wradr)
(wradr)
rddata
Header 49H: Interleaved A-D-D-D Sequence
This sequence (header 49H) allows in front of the A-D-D-D write access an interleaved
A-D-A-D read access. This mode is useful for reading status information before writing
to the HDLC XFIFO. The termination condition of the read access is the reception of the
wradr. The sequence can have any length and is terminated by the rising edge of the CS
line.
Example for a read/write access with header 49H:
SDR
header
SDX
Data Sheet
rdadr
rdadr
rddata
wradr
wrdata
wrdata
wrdata
(wradr)
(wradr)
(wradr)
rddata
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2.1.2
Interrupt Structure and Logic
Special events in the SCOUT-DX are indicated by means of a single interrupt output,
which requests the host to read status information from the SCOUT-DX or transfer data
from/to the SCOUT-DX.
Since only one INT request output is provided, the cause of an interrupt must be
determined by the host reading the interrupt status registers of the SCOUT-DX.
The structure of the interrupt status registers is shown in figure 9.
MSTI
STOV21
STOV20
STOV11
STOV10
STI21
STI20
STI11
STI10
MASK
ISTA
ST
CIC
TIN
WOV
TRAN
MOS
HDLC
ST
CIC
TIN
WOV
TRAN
MOS
HDLC
INT
STI
STOV21
STOV20
STOV11
STOV10
STI21
STI20
STI11
STI10
ASTI
ACK21
ACK20
ACK11
ACK10
CIC0
CIC1
CIR0
CI1E
CIX1
RME
RPF
RFO
XPR
RME
RPF
RFO
XPR
XMR
XDU
XMR
XDU
MASKH
ISTAH
MASKTR
LD
RIC
ISTATR
LD
RIC
MRE
MDR
MER
MIE
MDA
MAB
MOSR
MOCR
Figure 9
SCOUT-DX Interrupt Status Registers
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PSB 21373
Five interrupt bits in the ISTA register point at interrupt sources in the HDLC Controller
(HDLC), Monitor- (MOS) and C/I- (CIC) handler, the transceiver (TRAN) and the
synchronous transfer (ST). The timer interrupt (TIN) and the watchdog timer overflow
(WOV) can be read directly from the ISTA register. All these interrupt sources are
described in the corresponding chapters. After the SCOUT-DX has requested an
interrupt by setting its INT pin to low, the host must read first the SCOUT-DX interrupt
status register (ISTA) in the associated interrupt service routine. The INT pin of the
SCOUT-DX remains active until all interrupt sources are cleared by reading the
corresponding interrupt register. Therefore it is possible that the INT pin is still active
when the interrupt service routine is finished.
Each interrupt indication of the interrupt status registers can selectively be masked by
setting the respective bit in the MASK register.
For some interrupt controllers or hosts it might be necessary to generate a new edge on
the interrupt line to recognize pending interrupts. This can be done by masking all
interrupts at the end of the interrupt service routine (writing FFH into the MASK register)
and write back the old mask to the MASK register.
Data Sheet
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PSB 21373
2.1.3
Microcontroller Clock Generation
The microcontroller clock is provided by the pin MCLK. Five clock rates are selectable by
a programmable prescaler (see chapter clock generation figure 73) which is controlled
by the MODE1.MCLK bits corresponding following table. By setting the clock divider
selection bit (MODE1.CDS) a doubled MCLK frequency is available.
The possible MCLK frequencies are listed in table 4.
Table 4
MCLK Frequencies
MCLK
Bits
MCLK Frequency
with MODE1.CDS = ’0’
MCLK Frequency
with MODE1.CDS = ’1’
’00’
3.84 MHz (default)
7.68 MHz (default)
’01’
0.96 MHz
1.92 MHz
’10’
7.68 MHz
15.36 MHz
’11’
disabled
disabled
The clock rate is changed after CS becomes inactive.
Data Sheet
-31
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PSB 21373
2.2
IOM-2 Interface
The SCOUT-DX supports the IOM-2 interface in terminal mode with single clock and
double clock. The IOM-2 interface consists of four lines: FSC, DCL, DD and DU. The
rising edge of FSC indicates the start of an IOM-2 frame. The FSC signal is generated
by the receive DPLL which synchronizes to the received line frame. The DCL and the
BCL output clock signals synchronize the data transfer on both data lines. The DCL is
twice the bit rate, the BCL output rate is equal to the bit rate. The bits are shifted out with
the rising edge of the first DCL clock cycle and sampled at the falling edge of the second
clock cycle. The BCL clock together with the two serial data strobe signals (SDS1,
SDS2) can be used to connect time slot oriented standard devices to the IOM-2
interface.
The IOM-2 interface can be enabled/disabled with the DIS_IOM bit in the IOM_CR
register. The BCL clock output can be enabled separately with the EN_BCL bit.
The clock rate or frequency respectively of the IOM-signals in TE mode are:
DD, DU: 768 kbit/s
DCL: 1536 kHz (double clock rate); 768 kHz (single clock rate if DIS_TR = ’1’)
FSC: 8 kHz.
If the transceiver is disabled (TR_CONF.DIS_TR) the DCL and FSC pins become input
and the HDLC and codec parts can still work via IOM-2. In this case it can be selected
with the clock mode bit (IOM_CR.CLKM) between a double clock and a single clock
input.
Note: One IOM-2 frame has to consist of a multiple of 16 (8) DCL clocks for a double
(single) clock selection.
FSC
DCL
BCL
bcl
Figure 10 Clock waveforms
Data Sheet
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PSB 21373
2.2.1
IOM-2 Frame Structure
The frame structure on the IOM-2 data ports (DU,DD) in IOM-2 terminal mode is shown
in figure 11.
Figure 11
IOM-2 Frame Structure in Terminal Mode
The frame is composed of three channels
• Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR
programming channel (MON0) and a command/indication channel (CI0) for control
and programming of the layer-1 transceiver.
• Channel 1 contains two 64-kbit/s intercommunication channels (IC) plus a MONITOR
and command/indicate channel (MON1, CI1) to program or transfer data to other IOM2 devices.
• Channel 2 is used for the TlC-bus access. Additionally channel 2 supports further IC
and MON channels.
Note: Each octett related to any integrated functional block can be programmed to any
timeslot (see chapter 7.3.2) except the C/I0- and D- channels that are always
related to timeslot 0.
Data Sheet
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2.2.2
IOM-2 Handler
The IOM-2 handler offers a great flexibility for handling the data transfer between the
different functional units of the SCOUT-DX and voice/data devices connected to the
IOM-2 interface. Additionally it provides a microcontroller access to all time slots of the
IOM-2 interface via the four controller data access registers (CDA). Figure 12 shows the
architecture of the IOM-2 handler. For illustrating the functional description it contains all
configuration and control registers of the IOM-2 handler. A detailed register description
can be found in chapter 7.3
The PCM data of the functional units
• Codec (CO)
• Transceiver (TR) and the
• Controller data access (CDA)
can be configured by programming the time slot and data port selection registers
(TSDP). With the TSS bits (Time Slot Selection) the PCM data of the functional units can
be assigned to each of the 12 PCM time slots of the IOM-2 frame. With the DPS bit (Data
Port Selection) the output of each functional unit is assigned to DU or DD respectively.
The input is assigned vice versa. With the control registers (CR) the access to the data
of the functional units can be controlled by setting the corresponding control bits (EN,
SWAP).
To avoid data collisions it has to be noticed that the C/I and D channels of the enabled
transceiver are always related to time slot 3. If the monitor handler is enabled its data is
related to time slot TS (2, 6 or 10) and the appropriate MR and MX bits to time slot TS+1
depending on the MCS bits of register MON_CR.
The IOM-2 handler provides also access to the
• MONITOR channel (MON)
• C/I channels (CI0,CI1)
• TIC bus (TIC) and
• D- and B-channel for HDLC control
The access to these channels is controlled by the registers HCI_CR and MON_CR.
The IOM-2 interface with the two Serial Data Strobes (SDS1,2) is controlled by the
control registers IOM_CR, SDS1_CR and SDS2_CR.
The reset configuration of the SCOUT-DX IOM-2 handler corresponds to the defined
frame structure and data ports in IOM-2 terminal mode (see figure 11).
Data Sheet
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35
IOMHAND
CO10R
CO11R
CO20R
CO21R
CO10X
CO11X
CO20X
CO21X
x,y = 1 or 2
MSTI
ASTI
STI
CDA_CRx
CDA_TSDPxy
STI)
MCDA
CDA20
CDA21
EN)
CO_CR
CDA11
(TSS, DPS,
TBM, MCDA,
EN, SWAP,
(TSDP, DPS,
Data Access
Control
C D A D a ta
CO_TSDPxy
CDA10
Register
CDA
Access (CDA)
Codec
Data
Control
Controller Data
DD
DU
(EN, OD)
Handler
MON
TIC
MON_CR IOM_CR
Control
Monitor TIC Bus
Data
Disable
(DPS,EN (TIC_DIS)
MCS)
SDS1 SDS2
CI0
(EN, TLEN, TSS)
Data
IOM-2 Interface
M onitor D ata
Microcontroller Interface
SDS1/2_CR
IOM_CR
T IC B us D a ta
IOM-2 Handler
C o de c D a ta
FSC DCL BCL
C I0 D ata
DD
CI1
HDLC FIFO
HCI_CR
Control
Control
HDLC
C/I1
D-, BData
Data
(DPS,EN)
(EN)
C I1 D ata
Data Sheet
D /B 1/B 2 D ata
DU
DD
DU
C /IO - D ata
Control
B 1/B 2 /D - D a ta
TR_CR
TR_TSDP_B2
TR_TSDP_B1
EN)
(TSS, DPS,
Access
Data
Transceiver
TR_B1_X
TR_B2_R
TR_B1_R
TR_D_R
TR_D_X
TR_B2_X
PSB 21373
.
Figure 12
Architecture of the IOM Handler
2002-05-13
T ra n s c e ive r
D a ta (T R )
C o d e c D a ta
(C O )
PSB 21373
2.2.2.1
Controller Data Access (CDA)
The IOM-2 handler provides with his four controller data access registers (CDA10,
CDA11, CDA20, CDA21) a very flexible solution for the access to the 12
IOM-2 time slots by the microcontroller.
The functional unit CDA (controller data access) allows with its control and configuration
registers
• looping of up to four independent PCM channels from DU to DD or vice versa over the
four CDA registers
• shifting or switching of two independent PCM channels to another two independent
PCM channels on both data ports (DU, DD)
• monitoring of up to four time slots on the IOM-2 interface simultaneously
• microcontroller read and write access to each PCM channel
The access principle which is identical for the two channel register pairs CDA10/11 and
CDA20/21 is illustrated in figure 13. The index variables x,y used in the following
description can be 1 or 2 for x, and 0 or 1 for y. The prefix ’CDA_’ from the register names
has been omitted for simplification.
To each of the four CDAxy data registers a TSDPxy register is assigned by which the
time slot and the data port can be determined. With the TSS (Time Slot Selection) bits a
time slot from 0...11 can be selected. With the DPS (Data Port Selection) bit the output
of the CDAxy register can be assigned to DU or DD respectively. The time slot and data
port for the output of CDAxy is always defined by its own TSDPxy register. The input of
CDAxy depends on the SWAP bit in the control registers CRx.
If the SWAP bit = ’0’ the time slot and data port for the input and output of the CDAxy
register is defined by its own TSDPxy register. The data port for the CDAxy input is vice
versa to the output setting for CDAxy.
If the SWAP bit = ’1’, the input port and time slot of the CDAx0 is defined by the TSDP
register of CDAx1 and the input port and time slot of CDAx1 is defined by the TSDP
register of CDAx0.
The input and output of every CDAxy register can be enabled or disabled by setting the
corresponding EN (-able) bit in the control register CDAx_CR. If the input of a register is
disabled the output value in the register is retained.
Data Sheet
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2002-05-13
PSB 21373
.
TSa
TSb
DU
Control
Register
CDAx0
0
1
1
Time Slot
Selection (TSS)
Enable
input
output
(EN_I1)
(EN_O1)
Input
Swap
(SWAP)
1
1
1
1
CDAx1
1
1
0
CDA_TSDPx1
1
0
Data Port
Selection (DPS)
Time Slot
Selection (TSS)
CDA_CRx
0
Enable
output
input
(EN_O0) (EN_I0)
Data Port
Selection (DPS)
CDA_TSDPx0
1
DD
TSa
TSb
x = 1 or 2; a,b = 0...11
IOM_HAND
Figure 13
Data Access via CDAx0 and CDAx1 register pairs
2.2.2.1.1
Looping and Shifting Data
Figure 14 gives examples for typical configurations with the above explained control and
configuration possibilities with the bits TSS, DPS, EN and SWAP in the registers
TSDPxy or CDAx_CR:
a) looping IOM-2 time slot data from DU to DD or vice versa (SWAP = ’0’)
b) shifting data from TSa to TSb on DU and DD (SWAP = ’1’)
c) switching data from TSa (DU) to TSb(DD) and TSb (DU) to TSa (DD)
Data Sheet
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PSB 21373
a) Looping Data
TSa
TSb
CDAx0
CDAx0
.TSS: TSa
TSb
.DPS ’0’
’1’
.SWAP
’0’
DU
DD
b) Shifting Data
TSa
TSb
DU
CDAx0
CDAx0
DD
.TSS: TSa
TSb
.DPS ’0’
’1’
.SWAP
’1’
c) Switching Data
TSa
TSb
CDAx0
CDAx0
.TSS: TSa
.DPS ’0’
.SWAP
TSb
’0’
DU
DD
.x = 1 or 2
’1’
Figure 14
Examples for Data Access via CDAxy Registers
a) Looping Data
b) Shifting Data
c) Switching Data
Data Sheet
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PSB 21373
2.2.2.1.2
Monitoring Data
Figure 15 gives an example for monitoring of two IOM-2 time slots each on DU or DD
simultaneously. For monitoring on DU and/or DD the channel registers with even
numbers (CDA10, CDA20) are assigned to time slots with even numbers TS(2n) and the
channel registers with odd numbers (CDA11, CDA21) are assigned to time slots with odd
numbers TS(2m+1) (n,m = 0...5). The user has to take care of this restriction by
programming the appropriate time slots.
.
a) Monitoring Data
EN_O: ’0’
CDA_CR1. EN_I: ’1’
DPS: ’0’
TSS: TS(2n)
’0’
’1’
’0’
TS(2m+1)
DU
CDA10
CDA11
CDA20
CDA21
TSS: TS(2n)
’1’
DPS:
CDA_CR2.
EN_I: ’1’
EN_O: ’0’
TS(2m+1)
’1’
’1’
’0’
DD
n,m = 0...5
Figure 15
Example for Monitoring Data
2.2.2.1.3
Monitoring TIC Bus
Monitoring the TIC bus (TS11) is handled as a special case. The TIC bus can be
monitored with the registers CDAx0 by setting the EN_TBM (Enable TIC Bus Monitoring)
bit in the control registers CRx. The TSDPx0 must be set to 08h for monitoring from DU
or 88h for monitoring from DD respectively.
Data Sheet
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2.2.2.1.4
Synchronous Transfer
While looping, shifting and switching the data can be accessed by the controller between
the synchronous transfer interrupt (STI) and the status overflow interrupt (STOV).
The microcontroller access to the CDAxy registers can be synchronized by means of
four programmable synchronous transfer interrupts (STIxy) and synchronous transfer
overflow interrupts (STOVxy) in the STI register.
Depending on the DPS bit in the corresponding CDA_TSDPxy register the STIxy is
generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock after the selected time slot
(CDA_TSDPxy.TSS). One BCL clock is equivalent to two DCL clocks.
A non masked synchronous transfer overflow (STOVx0y0) interrupt is generated if the
appropriate STIx1y1 is not acknowledged in time. The STIx1y1 is acknowledged in time if
bit ACKx1y1 in the ASTI register is set to ’1’ one BCL clock (for DPS=’0’) or zero BCL
clocks (for DPS=’1’) before the time slot which is selected for the appropriate STOVx0y0.
If STIx1y1 and STOVx1y1 are not masked STOVx1y1 is only related to STIx1y1 (see
example a), c) and d) of figure 17).
If STIx1y1 is masked but STOVx1y1 is not masked, STOVx0y0 is related to each enabled
STIxy (see example b) and d) of figure 17).
Setting the corresponding bits in the MSTI (Mask Synchronous Transfer Interrupts)
register masks the STIxy and the STOVxy interrupt. The interrupt structure of the
synchronous transfer is shown in figure 16. Examples of the described synchronous
transfer interrupt controlling are illustrated in Figure 17. A read to the STI register clears
the STIxy and STOVxy interrupts.
.
INT
ST
CIC
TIN
WOV
TRAN
MOS
HDLC
ST
CIC
TIN
WOV
TRAN
MOS
HDLC
MASK
ISTA
STOV21
STOV20
STOV11
STOV10
STI21
STI20
STI11
STI10
MSTI
STOV21
STOV20
STOV11
STOV10
STI21
STI20
STI11
STI10
STI
ACK21
ACK20
ACK11
ACK10
ASTI
Figure 16
Interrupt Structure of the Synchronous Data Transfer
Data Sheet
40
2002-05-13
PSB 21373
.
: STI interrupt generated
: STOV interrupt generated for a not acknowledged STI interrupt
a) Interrupts for data access to time slot 0 (B1 after reset), MSTI.STI10 and MSTI.STOV10 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
'0'
'0'
11
TS1
'1'
'1'
TS11 TS0 TS1
21
TS5
'1'
'1'
TS2 TS3
TS4 TS5
20
TS11
'1'
'1'
TS6 TS7 TS8 TS9 TS10 TS11 TS0
b) Interrupts for data access to time slot 0 (B1 after reset), STOV interrupt used as flag for "last possible CDA
access"; MSTI.STI10 and MSTI.STOV20 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
'0'
'1'
11
TS1
'1'
'1'
TS11 TS0 TS1
21
TS5
'1'
'1'
TS2 TS3
TS4 TS5
20
TS11
'1'
'0'
TS6 TS7 TS8 TS9 TS10 TS11 TS0
c) Interrupts for data access to time slot 0 and 1 (B1 and B2 after reset), MSTI.STI10, MSTI.STOV10,
MSTI.STI11 and MSTI.STOV11 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
'0'
'0'
11
TS1
'0'
'0'
TS11 TS0 TS1
21
TS5
'1'
'1'
TS2 TS3
TS4 TS5
20
TS11
'1'
'1'
TS6 TS7 TS8 TS9 TS10 TS11 TS0
d) Interrupts for data access to time slot 0 (B1 after reset), STOV20 interrupt used as flag for "last possible CDA
access", STOV10 interrupt used as flag for "CDA access failed"; MSTI.STI10, MSTI.STOV10 and
MSTI.STOV20 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
'0'
'0'
11
TS1
'1'
'1'
TS11 TS0 TS1
21
TS5
'1'
'1'
TS2 TS3
TS4 TS5
20
TS11
'1'
'0'
TS6 TS7 TS8 TS9 TS10 TS11 TS0
sti_stov
Figure 17
Examples for the Synchronous Transfer Interrupt Control with one enabled STIxy
Data Sheet
41
2002-05-13
PSB 21373
Figure 18 shows the timing of looping TSa on DU to TSa on DD (a = 0...11) via CDAxy
register. TSa is read in the CDAxy register from DU and is written one frame later on DD.
.
a = 0...11
FSC
DU
TSa
TSa
WR
RD
DD
TSa
STOV
µC *)
STI
ACK
STI
CDAxy
TSa
*) if access by the µC is required
Figure 18
Data Access when Looping TSa from DU to DD
Data Sheet
42
2002-05-13
PSB 21373
Figure 19 shows the timing of shifting data from TSa to TSb on DU(DD). In figure 19a)
shifting is done in one frame because TSa and TSb didn’t succeed direct one another
(a,b = 0...9 and b ≥ a+2). In figure 19b) shifting is done from one frame to the following
frame. This is the case when the time slots succeed one other (b = a+1) or b is smaller
than a (b < a).
a) Shifting TSa → TSb within one frame
(a,b: 0...11 and b ≥ a+2)
FSC
DU
(DD)
TSa
TSb
TSa
µC
ACK
*)
STI
STOV
WR
STI
RD
CDAxy
b) Shifting TSa → TSb in the next frame
(a,b: 0...11 and (b = a+1 or b
